1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a layout pattern of a memory cell array region having a memory cell and a peripheral region thereof.
2. Description of the Background Art
A memory cell array structure of a conventional semiconductor device having a DRAM and the like includes a plurality of memory cells arranged in a matrix. One power wiring is inserted and provided in every predetermined number of memory cells. The power wiring is a power wiring for power supply which serves to enhance supply capabilities of a source potential or a ground potential (GND) by relatively increasing a formation width, and is usually formed of metal such as aluminum, copper or the like. The power wiring is formed in a power wiring region which is specially provided for forming only the power wiring.
In the power wiring region, an element such as a transistor is not formed in an area positioned under the power wiring. Therefore, a difference between coarse and fine portions is made on a mask pattern for forming a memory cell between the memory cell array region where a plurality of memory cells are formed and the power wiring region. In the mask pattern for forming a memory cell, a pattern width of the power wiring region where the memory cell is not formed at all becomes much larger than a pattern width of the memory cell array region.
In the case where a resist is subjected to patterning with a mask pattern in which the difference between coarse and fine portions is thus made remarkably after an exposing step using a photomask, there has been the following drawback. More specifically, uneven irradiation is generated by various phenomena such as diffraction interference of light and the like so that a pattern boundary becomes blurred. For this reason, the patterning cannot be performed with high precision. Thus, the patterning controllability of a memory cell is deteriorated.
Moreover, a difference between coarse and fine portions is usually made on the mask pattern for forming a memory cell between the memory cell array region and a peripheral portion thereof (where the memory cell is not formed). Therefore, there has been the drawback that the patterning controllability of the memory cell is deteriorated as described above.